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MX9691L
SINGLE CHIP SOLID STATE DISK CONTROLLER
1. FEATURE
Host Interface * PCMCIA 2.1 and PC Card ATA standard compatible. - Memory mapped or I/O operation. * Compatible with all PC Card Services and Socket Service. * Fast ATA host-to-buffer burst transfer rates up to 20MB/sec. which support PIO mode 4(16.6MB/sec) and DMA mode 2(16.6MB/sec). * Automatic sensing of PCMCIA or True IDE host inter face. * Integrated PCMCIA attribute memory of 256 bytes (CIS) - CIS and Buffer RAM use same SRAM area to simplify internal bus design * PCMCIA card configuration register support. * Polarity control for Host reset signal. * PCMCIA twin card support. * PCMCIA based ATA address decode support. * Emulate the IBM task file for PC/AT. * Separate status for Host reset signal and Host program reset. * Separate Host and Disk interrupt pins. Flash Memory Interface * Support all the control signals to execute read/ write/ erase operation for flash memory. * Flexible Disk Capacity Configuration for series type or linear type flash memory - Upto 32MB(unformatted) capacity for 16 pcs. 16Mbit linear type flash memory. - Upto 1GB(unformatted) capacity for 32 pcs. 256Mbit series type flash memory. * Flash Memory Power Down or write protect control support. * Flash Memory Ready/Busy status detect. * Inverted data bus control to reduce flash memory program/erase operation in DOS FAT and ECC code field. * Optional store firmware in flash memory array w/o external ROM while MXIC's MX29F1610(linear type) used. - Allow code fetch in Shadow ROM during flash memory program or erase. Buffer RAM Manager * Dual port circular Buffer RAM control * 1KB data Buffer RAM. * Automatically correct error data in Buffer RAM. - Single word error correct and double word detect. * Provide logic to speed up Buffer RAM access. * Support 8 bit as well as 16 bit transfer on host bus. DSP core * High performance MX93011 DSP (21Mips) core. * 4KB Internal RAM(direct access). * 2KB Internal expansion RAM(indirect access) for store data or shadow ROM space. * ICE debugging mode supported to ease system verification. * Lower power and automatic power saving operation. - Automatic Standby Mode. (Operating Current < 10mA, VCC=5.5V), wake-up by interrupt signal. - Very Low Operating Current Sleep Mode. (<1mA,VCC=5.5V), wake-up by Host reset signal or Host program reset or ATA command asserted by host. Technology * * * * 128 pin LQFP(14X14X1.4 mm3) 128 pin TQFP(14X14X1.0 mm3) 0.6um Low-power, High-speed CMOS technology. 5Volt 10% or 3.3Volt 5%.
Utility Support * Provide integrated test environment with 82365SLcompatible adaptor. * Firmware upload from host and allows easy upgrade for custom feature. * Physical devices test cover basic PCB test after assembly and more detial analysis. * Logical sector test cover SSD functionality and data transfer test.
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MX9691L
2. GENERAL DESCRIPTION
The Macronix's Solid State Disk controller MX9691L is a wide-range supply voltage(3.3Volt~5Volt) and fully integrated flash memory controller that provides all the control logic for PCMCIA/True IDE host and flash memory. The MX9691L combines 1KB dual-port buffer and buffer manager, integrated MX93011 DSP core, and a complete host interface for both the PC Card ATA and True IDE standard. The MX9691L provides flexible disk capacity configuration and supports all the control signals to execute read/write/erase operation for linear type or series type flash memory chip. It is typically configured with up to 32MB(unformatted) capacity for 16 pcs. 16Mbit linear flash memory or 1GB(unformatted) capacity for 32 pcs. 256Mbit series type flash memory while capacity extention mode is enabled for series type flash memory used. The MX9691L also provides flexible architecture to implement defect management and wear-leveling by firmware for series type or linear type flash memory. In linear mode, the linear type 16 Mbit flash memory is supported, such as MXIC's MX29F1610 etc. In flash memory interface there are two banks of flash memory to be provided. Each bank support 8 pcs. flash memory when linear type flash memory is used. In series mode, the series type 16MBit/32Mbit/64Mbit/256Mbit flash memory is suppor ted, such as Toshiba's TC5816FT/TR or TC58V32FT, Samsung's KM29N16000T/R or KM29N32000TS/RS etc. Each bank support or 16 pcs. flash memory when series type flash memory is used. The MX9691L is fully compliant with the PC Card ATA specification. It includes 256 bytes of integrated attribute memory(for the required Card Information Structure) and four Card Configuration registers. The PCMCIA device driver can access the MX9691L's ATA command block through four different modes by writing the different modes by writing the configuration index of the attribute memory configuration option register.
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3. PIN CONFIGURATION
INPACK#
HRESET
HCE1#
HCE2#
IREQ#
HWE#
GNDP
VCCP
HOE#
HD11
HD12
HD13
HD14
HD15
IOW#
HA10
WAIT 98
IOR#
GND
VCC
HD3
HD4
HD5
HD6
HD7
HA9
HA8
HA7
HA6
HA5
HA4 99
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
97
HA3
FA16 FA15 A14 A13 A12 LED# GNDP A11 A10 A9 A8 FA19 FRY/FBY# INT1# NMI# HOLD# VCCP WRFLASH0# WRFLASH1# FA18 FA17 A15 A7 A6 GNDP A5 A4 A3 A2 A1 A0 WP#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
HA2 REG# HA1 SPKR HA0 GNDP STSCHG HD0 HD8 HD1 HD9 HD2 HD10 IOIS16# PWR_RST TEST VCCP X1 X2 GNDP ROMWR# ROMCS# SCTRL# HLDA# VCCX32 SWAIT# NC GNDX32 DCE# PCE# WR# RD#
MX9691L
GNDP
VCCP
GND
VCC
RDFLASH0#
FCE7#
FCE2#
FCE1#
FCE0#
FCE6#
FCE5#
FCE4#
FCE3#
RDFLASH1#
GNDP
D7
D6
D5
D4
D3
D2
D1
D0
D8
D9
D10
D11
D12
D13
D14
D15
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4. PIN DESCRIPTION
Host Interface Symbol HA[10:0] No. 92,94, 96-97,99 101-103, 106,109, 113 84-89, 116-117, 121-128 104,111 Type I (CMOS) Description Host address line 10-0. These pins include internal pull-up resistors.
HD[15:0]
I/O (TTL) I (CMOS) I (CMOS) I (CMOS)
Host data line 15-0. These pins include internal bus holder circuit that keep previous state when tri-state. Host memory read/write/mode select : Both pins include internal pull-up resistors that is default in PCMCIA mode. Host I/O access. Both pins include internal pull-up resistor. The host reset signal, when active, initializes the control/ status registers and stops any command in process. In PCMCIA mode, the signal is active high. In True IDE mode, this signal is active low. This signal include internal pull-down resistor. WAIT or INPUT CHANNEL READY : In both PCMCIA and True IDE modes, this signal holds host transfers until the controller is ready to respond. READY/BUSY or HOST INTERRUPT : In PCMCIA mode, this signal has two functions. In PCMCIA common memory mode, this signal is ready/busy. It is asserted busy by the reset logic, and can be deasserted by the DSP or represents the ready/busy bit of ATA status register. In PCMCIA I/O mode, this signal is IREQ#. In True IDE mode, this active high signal is HOSTINT, which, when enable, send an interrupt to the host.
HOE#,HWE#
IOR#,IOW# HRESET/HRESET#
107,110 100
WAIT/ IOCHRDY
98
O,OD (CMOS) O, Z (CMOS)
RDY/BSY#/ IREQ#/ HOSTINT
119
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Symbol WP/IOCS16# No. 83 Type O,OD (CMOS) Description WRITE PROTECT or 16-bit I/O TRANSFER : In PCMCIA mode, this bit has two functions. In PCMCIA common-memory mode,this signal indicates write protect. In PCMCIA I/O mode, when IOIS16# is asserted low, it indicates that a 16-bit data transfer is active on PCMCIA bus. In True IDE mode, the IOCS16# signal indicates that a 16-bit buffer transfer is active on the host bus. This open drain signal is only driven on assertion(low). Attribute memory and I/O select : In PCMCIA mode, this signal is used to select attribute memory and I/O space. In True IDE mode, this signal is used during DMA with the DREQ, IOR# and IOW# signals to transfer data between the host and the MX9691L. This pin includes an internal pull-up resistor. Card enable 1 or Chip select 0:In PCMCIA mode,this signal is card enable 1. This signal can enable either even or odd numbered-address bytes onto HD7:0. In True IDE mode, this signal accesses the MX9691 command block registers. This input is ignored during DMA data transfer, i.e. when the DACK# signal is low. This pin includes an internal pull-up resistor. Card enable 2 or Chip select 1: In PCMCIA mode,this signal is card enable 2. This signal can enable odd numbered-address bytes onto HD15:8. In True IDE mode, this signal accesses the MX9691L control block registers. This pin includes an internal pull-up resistor. Input Acknowledge or DMA request :In PCMCIA mode, this signal is asserted when the MX9691 is configured to respond to I/O card read cycles at all addresses. In True IDE mode, this signal is DREQ and is issued during DMA transfers to indicate that the MX9691L is ready for DMA transfer. Speaker or slave present : In PCMCIA mode, the output-enable for this signal is controlled by the card configuration registers. In True IDE mode, this signal is used as the slave-present detector. Status change or pass diagnostics :In PCMCIA mode, this signal is used to indicate changes in the RDY/BSY#,WP signals in card configuration registers. In True IDE mode, this active low signal is used between two embedded ATA drive to indicate that the drive in slave mode has passed diagnostics.
REG#/DACK#
95
I (CMOS)
HCE1#/ CS1FX#
115
I (CMOS)
HCE2#/ CS3FX#
114
I (CMOS)
INPACK#/ DREQ
118
O (CMOS)
SPKR/DASP#
93
I/O (CMOS)
STSCHG/ PDIAG#
90
I/O (CMOS)
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External Memory Bus Interface Symbol D[15:0] A[15:0] No. 33-37,39-41, 55-58,60-63 3-5,8-11, 22-24,26-31 Type I/O (CMOS) I/O (CMOS) Description DSP IO/RAM/ROM/FLASH memory array external data bus. These pins include internal pull- up resistors. In Free-run mode, these signals are output that used as DSP IO/RAM/ROM external address. A14-A0 are used for flash memory array address also. In upgrade mode, these address are used for ROM address that controlled by CYH,CYL registers. In ICE-debugging mode,these address are input, asserted by DSP ICE(external MX93011 DSP). And the internal DSP is disabled at this time. These pins include internal pull-up resistors. In Free-run mode, this signal is output that is used as external program chip enable. In upgrade mode, this signal is drived to high. In ICE-debugging mode, this signal is input, asserted by DSP ICE(external MX93011 DSP). And the internal DSP is disabled at this time. This pin includes a bus holder circuit. In Free-run mode, this signal is output that is used as external data chip enable. In upgrade mode, this signal is drived to high. In ICE-debugging mode, this signal is input, asserted by DSP ICE(external MX93011 DSP). And the internal DSP is disabled at this time. This pin includes a bus holder circuit. In Free-run mode, this signal is output that is used as DSP IO/RAM/ROM external read. In upgrade mode, this signal is output and asserted when the data register is read in host interface. In ICE-debugging mode, this signal is input, as serted by DSP ICE(external MX93011 DSP). And the internal DSP is disabled at this time. This pin includes a bus holder circuit. In Free-run mode, this signal is output that is used as DSP IO/RAM/ROM external write. In upgrade mode, this signal is drived to high. In ICE-debugging mode, this signal is input, asserted by DSP ICE(external MX93011 DSP). And the internal DSP is disabled at this time. This pin includes a bus holder circuit. Non maskable interrupt pin. This pin includes an pull-up resistor. In Free-run mode, this signal is input that is used as interrupt pin. Interrupt will be internally asserted also when data transfer done, or command end. In ICE-debugging mode, this signal is output and asserted when data transfer done, or command end. This pin includes an pull-up resistor.
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PCE#
67
I/O (TTL)
DCE#
68
I/O (TTL)
RD#
65
I/O (TTL)
WR#
66
I/O (TTL)
NMI# INT1#
15 14
I (CMOS) I/O (CMOS)
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Symbol HOLD# No. 16 Type I/O (CMOS) Description In Free-run mode, this signal is input that is used as holding DSP clock down and release bus. Bus hold will be internally asserted also when upgrade mode enable. In ICE-debug ging mode, this signal is output and asserted when upgrade mode enable. This pin includes an pull-up resistor. In Free-run mode, this signal is output that is used as ack to HOLD# signal. This signal will be internally sent to PCMCIA/ ATA interface also when upgrade mode enable. In ICE-de bugging mode, this signal is input and ack to HOLD# when upgrade mode enable. Sleep control, this pin can be directly asserted to low while power down bit is set by DSP. This pin is connected to external RC circuit. Default inactive (Logic High). In ICE-debugging mode, this signal is used to reset DSP.
HLDA#
73
I/O (CMOS)
XF#/SCTRL#
74
O (CMOS)
Flash Memory Interface
Symbol FA19/CLE No. 12 Type O (CMOS) Description In linear mode, this signal is used as flash memory chip high address line 19. In series mode, this signal is used as flash memory chip command latch enable. I/O In linear mode, this signal is used as flash memory chip high (CMOS) address line 18. In series mode, this signal is used as flash memory chip address latch enable. This signal is also used to select whether the MX9691 initializes in Free-run mode or in ICE-debugging mode at power-on reset. If this pin go high, then the MX9691L will switch to Free-run mode at power-on reset,and if this pin remains low, then the MX9691L will initializes in ICE-debugging mode. This pin includes an internal pull-up resistor. ICE-debugging mode select : ICEMODE=1 --> Free-run mode. ICEMODE=0 --> ICE-debugging mode. I/O(CMOS) This signal is used as flash memory chip high address line 17. This signal is also used to select whether the firmware store in linear type flash memory array or in separate external ROM at power-on reset. If this pin go high, then the firmware will be executed in linear type flash memory array, and if this pin remains low, then the firmware will be executed in separate external ROM. Store firmware in external ROM or linear type Flash memory array select: EROM = 0 --> Store in External ROM. EROM = 1 --> Store in flash memory array. This pin includes an internal pull-up resistor.
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FA18/ALE/ ICEMODE
20
FA17/EROM
21
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Symbol FA[16:15]/ ATADET[1:0] No. 1-2 Type I/O (CMOS) Description This signal is used as flash memory chip high address line 16-15. These signals are also used to select configuration in True IDE mode at power-on reset. ATADET1 is connected to DSP's IPT1. ATADET0 is connected to DSP's IPT0. VDD is connected to IPT2. Master/Slave selection in True IDE mode : ATADET1 ATADET0 mode selected 1 1 one drive 0 0 master of two drives 1 0 slave of two drives This power-on configuration can be accessed from PCMCIA/ ATA port 601Ch bit3-2. These pins include internal pull-up resistors. Flash memory ouptut enable 1 for bank1: This signal will be asserted by flash memory read operation when flash memory read address latch, port 601Dh bit 8= 1(i.e. FA23=1). Note: Flash memory access window is mapped to 32KW data and code space 8000h~ffffh. Flash memory ouptut enable 0 for bank0: This signal will be asserted by flash memory read operation when flash memory read address latch, port 601Dh bit 8 = 0(i.e. FA23=0). Flash memory write enable 1 for bank1: This signal will be asserted by flash memory write operation when flash memory write address latch, port 601Fh bit 8 = 1(i.e. FA23=1). Flash memory write enable 0 for bank0: This signal will be asserted by flash memory write operation when flash memory write address latch, port 601Fh bit 8 = 0(i.e. FA23=0).
RDFLASH1#
54
O (CMOS)
RDFLASH0#
42
O (CMOS)
WRFLASH1#
19
O (CMOS)
WRFLASH0#
18
O (CMOS)
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Symbol FCE[7:0]# No. 43-44, 46-47 49-52 Type O (CMOS) Description Flash memory chip enable 7-0 : In linear mode, These signals are decoded from port 601Dh bit 7-5 when flash memory read or port 601Fh bit 7-5 when flash memory write. Decoding combination : bit7 bit6 bit5 FCE[7:0]# 000 11111110 001 11111011 010 11101111 011 10111111 100 11111101 101 11110111 110 11011111 111 01111111 In series mode, These are decoded from port 601Dh bit 7-5 only when port 601Eh bit 2 is set. In linear mode, this signal is used as deep power-down control of flash memory chips of bank0. PWD0# is active low and also locks out erase or program operation providing data protection during power transitions. Power down pin PWD0# will be active if FA23=1. In series mode, this signal is used to protect the device from inadvertent programming or erasing. WP# is active low. In linear mode, this signal is used as deep power-down control of flash memory chips of bank1. PWD1# is active low and also locks out erase or program operation providing data protection during power transitions. Power down pin PWD0# will be active if FA23=0. In series mode,this signal is used to spare area control. SE# is active low. Flash memory Ready/busy input: This signal indicate the state of erase or program operation in flash memory chips.This pin includes an internal pull-up resistor.
PWD0#/WP#
32
O (CMOS)
PWD1#/SE#
64
O (CMOS)
FRY/FBY#
13
I (CMOS)
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Control ROM interface Symbol ROMCS#/ FWIN# No. 75 Type O (CMOS) Description ROM chip select/Flash memory data buffer enable : In Free-run mode, this signal is used as ROM chip enable if firmware that stored in external ROM. In ICE-debugging mode, this signal is used as flash memory data buffer (74640) enable if firmware that stored in flash memory array. ROM write enable/Flash memory data buffer direction control: In Free-run mode, this signal is used as ROM write enable if firmware that stored in external ROM. In ICE-debugging mode, this signal is used as flash memory data buffer (74640) direction control if firmware that stored in flash memory array.
ROMWR#/FDIR
76
O (CMOS)
Miscellaneous Symbol X1 X2 SWAIT# N.C. TEST No. 79 78 71 70 81 Type I O I(CMOS Schmitt) O I (CMOS) Description Crystal input. Crystal ouput. Sleep wait, this pin is connected to external RC circuit. No connect. This signal is used to select the main system clock, either from external clock source if this signal is high or from internal PLL circuit if this signal is low. This pin includes an internal pull-up resistor. Power on reset, CMOS Schmite-triggered: The MX9691L include debouncing circuit to stabilize internal DSP reset signal. LED output: This signal is connected to external LED in debugging system to indicate system status. The LED will be turn-on during reset. The contorl firmware will turn off the LED after H/W initialization and pass diagnostics. If system fail, the control firmware will flash the LED to indicate some error occur. This signal will be high if port 601Ch bit0 set to 1 or OPTR bit2 set to 1. 5 or 3.3 volt Power pin
PWR_RST#
82
I(CMOS Schmitt) O (CMOS)
LED#
6
VCC
GND
17,45,53, 72,80,105, 112 7,25,38, 48,59,69, 77,91,108, 120
Ground pin
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5. Functional and Operation Description
5-1. Block Diagram
Clock
External Memory Bus
Clock & Reset
MX93011 DSP CORE
4KB Internal RAM 2KB Internal RAM
Register Bank
Host Interface PCMCIA/ATA
PCMCIA/ATA interface
1KB Buffer RAM
Flash Memory Control
Flash Interface
256 Byte CIS RAM
Buffer RAM Control
ECC Control Logic
MX9691L Signal Chip Solid State Disk Controller
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5-2. System Memory Map Data Space : Address 0000h~007fh 0080h~07ffh 0800h~5fffh 6000h~63ffh 6400h~6fffh 7000h~73ffh 7400h~77ffh 7800h~7fffh 8000h~ffffh Program Space : Address 0000h~77ffh 7800h~7fffh 8000h~ffffh
Function & Usage Internal RAM (128W) to store control variables Internal RAM(1920W) for flash memory algorithm usage User define (22kW) I/O range(1kW): ATA CTL. use I/O range (6000h~601fh) User define (3kW) User define (1kW) Internal RAM (1kW) for expansion RAM or shadow ROM space ROM Data space(2kW) Flash memory access windows(32kW)
Function & Usage ROM program space (32kW) Unused Flash memory access windows(32kW)
5-3. Power-on detection * Store firmware in external ROM or Flash memory array : FA17/EROM = 0 --> Store in External ROM FA17/EROM = 1 --> Store in flash memory array * Master/Slave selection in True IDE mode : FA16/ATADET1 FA15/ATADET0 mode selected 1 1 one drive 0 0 master of two drives 1 0 slave of two drives Note : For some customers design the master/slave selection is selected by only one jumper that may be FA16 or FA15. It need to change firmware only. * ICE debugging mode select : FA18/ICEMDOE = 0 ---> ICE-debugging mode FA18/ICEMODE = 1---> Free-run mode, DSP fetch code from external memory bus and execute it. * Flash memory data buffer control ROMCS# is replaced by FWIN# if ICE-debugging mode & firmware in linear type flash memory array. ROMWR# is replaced by FDIR if ICE-debugging mode & firmware in linear type flash memory array. * PCMCIA mode or True IDE mode select HOE# Mode 0 True IDE mode 1 PCMCIA mode To enable True IDE mode this input should be grounded by the host.
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5-4. Decoding Configuration of all registers in Host interface * Common Momory Mode Decode Register Address CE1# CE2# REG# HA10 HA9:4 HA3:0 0 0 1 0 xh 000xb 0 1 1 0 xh 0000b 1 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 xh xh xh xh xh xh xh xh xh xh xh xh xh xh xh xh xh xh xh xh 0000b 0001b 0001b 001xb 0010b 0011b 0011b 010xb 0100b 0101b 0101b 011xb 0110b 0111b 0111b 100xb 1000b 1001b 1001b 110xb
0 0 0
1 0 1
1 1 1
0 0 0
xh xh xh
1101b 111xb 1110b
Register Read Enable HOE# =0 Read Data Register HD[15:0] Read Data HD[7:0] Even & Odd byte Error Status HD[15:8] Error Status HD[7:0] Error Status HD[15:8] Sector Count HD[7:0] Sector Number HD[15:8] Sector Count HD[7:0] Sector Number HD[7:0] Sector Number HD[15:8] Cyl. Low HD[7:0] Cly. High HD[15:8] Cyl. Low HD[7:0] Cly. High HD[7:0] Cly. High HD[15:8] Drive/Head HD[7:0] Ctl. Status HD[15:8] Drive/Head HD[7:0] Ctl. Status HD[7:0] Ctl. Status HD[15:8] Read Data Register HD[15:0] (Duplicate) Read Data HD[7:0] Even & Odd byte (Duplicate) Read Data HD[15:8] Odd byte (Duplicate) Read Data HD[7:0] Odd byte (Duplicate) Undefined HD[7:0] Error Status HD[15:8] (Duplicate) Error Status HD[7:0] (Duplicate) Alternate Ctl. Status HD[7:0] Drive/Head HD[15:8] Alternate Ctl. Status HD[7:0]
Register Write Enable HWE# = 0 Write Data Register HD[15:0] Write Data HD[7:0] Even & Odd byte Features HD[15:8] Features HD[7:0] Features HD[15:8] Sector Count HD[7:0] Sector Number HD[15:8] Sector Count HD[7:0] Sector Number HD[7:0] Sector Number HD[15:8] Cyl. Low HD[7:0] Cly. High HD[15:8] Cyl. Low HD[7:0] Cly. High HD[7:0] Cly. High HD[15:8] Drive/Head HD[7:0] Command HD[15:8] Drive/Head HD[7:0] Command HD[7:0] Command HD[15:8] Write Data Register HD[15:0] (Duplicate) Write Data HD[7:0] Even & Odd byte (Duplicate) Write Data HD[15:8] Odd byte (Duplicate) Write Data HD[7:0] Odd byte (Duplicate) Undefined HD[7:0] Features HD[15:8] (Duplicate) Features HD[7:0] (Duplicate) Device Ctl. HD[7:0] Undefined HD[15:8] Device Ctl. HD[7:0]
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0 1 0 0 0 1 1 Register Address 1 1 0 0 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 xh xh xh xh xh xh xh 1111b 1111b xxxxb xxx0b xxx1b xxx0b xxx1b Register Read Enable Drive/Head HD[7:0] Drive/Head HD[15:8] Read Data Register HD[15:0] Read Data HD[7:0] Even & Odd byte Read Data HD[7:0]Odd byte Read Data HD[15:8] Odd byte Read Data HD[15:8] Odd byte Register Write Enable Not Used Not Used Write Data Register HD[15:0] Write Data HD[7:0] Even & Odd byte Write Data HD[7:0]Odd byte Write Data HD[15:8] Odd byte Write Data HD[15:8] Odd byte
* Independent I/O Mode Decode Register Address CE2# REG# HA9:4 0 0 xh 1 0 xh 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 xh xh xh xh xh xh xh xh xh xh xh xh xh xh xh xh xh xh xh xh Register Read Enable IOR# =0 Read Data Register HD[15:0] Read Data HD[7:0] Even & Odd byte Error Status HD[15:8] Error Status HD[7:0] Error Status HD[15:8] Sector Count HD[7:0] Sector Number HD[7:0] Sector Number HD[15:8] Cyl. Low HD[7:0] Cly. High HD[7:0] Cly. High HD[15:8] Drive/Head HD[7:0] Ctl. Status HD[7:0] Ctl. Status HD[15:8] Read Data Register HD[15:0](Duplicate) Read Data HD[7:0] Even & Odd byte (Duplicate) Read Data HD[15:8] Odd byte (Duplicate) Read Data HD[7:0] Odd byte (Duplicate) Error Status HD[7:0](Duplicate) Alternate Ctl. Status HD[7:0] Drive/Head HD[7:0] Drive/Head HD[15:8] Register Write Enable IOW# = 0 Write Data Register HD[15:0] Write Data HD[7:0] Even & Odd byte Features HD[15:8] Features HD[7:0] Features HD[15:8] Sector Count HD[7:0] Sector Number HD[7:0] Sector Number HD[15:8] Cyl. Low HD[7:0] Cly. High HD[7:0] Cly. High HD[15:8] Drive/Head HD[7:0] Command HD[7:0] Command HD[15:8] Write Data Register HD[15:0](Duplicate) Write Data HD[7:0] Even & Odd byte (Duplicate) Write Data HD[15:8] Odd byte (Duplicate) Write Data HD[7:0] Odd byte (Duplicate) Features HD[7:0](Duplicate) Device Ctl. HD[7:0] Not Used Not Used
CE1# 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1
HA3:0 0000b 0000b 0000b 0001b 0001b 0010b 0011b 0011b 0100b 0101b 0101b 0110b 0111b 0111b 1000b 1000b 1001b 1001b 1101b 1110b 1111b 1111b
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* Primary ATA Mode Decode Register Address CE2# REG# HA9:0 0 0 1F0h 1 0 1F0h 0 0 1F0h 1 0 1F1h 0 0 1F1h 1 0 1F2h 1 0 1F3h 0 0 1F3h 1 0 1F4h 1 0 1F5h 0 0 1F5h 1 0 1F6h 1 0 1F7h 0 0 1F7h 1 0 3F6h 1 0 3F7h 0 0 3F7h Register Read Enable IOR# =0 Read Data Register HD[15:0] Read Data HD[7:0]Even & Odd byte Error Status HD[15:8] Error Status HD[7:0] Error Status HD[15:8] Sector Count HD[7:0] Sector Number HD[7:0] Sector Number HD[15:8] Cyl. Low HD[7:0] Cly. High HD[7:0] Cly. High HD[15:8] Drive/Head HD[7:0] Ctl. Status HD[7:0] Ctl. Status HD[15:8] Alternate Ctl. Status HD[7:0] Drive/Head HD[7:0] Drive/Head HD[15:8] Register Write Enable IOW# = 0 Write Data Register HD[15:0] Write Data HD[7:0]Even & Odd byte Features HD[15:8] Features HD[7:0] Features HD[15:8] Sector Count HD[7:0] Sector Number HD[7:0] Sector Number HD[15:8] Cyl. Low HD[7:0] Cly. High HD[7:0] Cly. High HD[15:8] Drive/Head HD[7:0] Command HD[7:0] Command HD[15:8] Device Ctl. HD[7:0] Not Used Not Used
CE1# 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1
* Secondary ATA Mode Decode Register Address CE1# CE2# 0 0 0 1 1 0 0 1 1 0 0 1 0 1 1 0 0 1 0 1 1 0 0 1 0 1 1 0 0 1 0 1 1 0
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REG# 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HA9:0 170h 170h 170h 171h 171h 172h 173h 173h 174h 175h 175h 176h 177h 177h 376h 377h 377h
Register Read Enable IOR# =0 Read Data Register HD[15:0] Read Data HD[7:0]Even & Odd byte Error Status HD[15:8] Error Status HD[7:0] Error Status HD[15:8] Sector Count HD[7:0] Sector Number HD[7:0] Sector Number HD[15:8] Cyl. Low HD[7:0] Cly. High HD[7:0] Cly. High HD[15:8] Drive/Head HD[7:0] Ctl. Status HD[7:0] Ctl. Status HD[15:8] Alternate Ctl. Status HD[7:0] Drive/Head HD[7:0] Drive/Head HD[15:8]
Register Write Enable IOW# = 0 Write Data Register HD[15:0] Write Data HD[7:0]Even & Odd byte Features HD[15:8] Features HD[7:0] Features HD[15:8] Sector Count HD[7:0] Sector Number HD[7:0] Sector Number HD[15:8] Cyl. Low HD[7:0] Cly. High HD[7:0] Cly. High HD[15:8] Drive/Head HD[7:0] Command HD[7:0] Command HD[15:8] Device Ctl. HD[7:0] Not Used Not Used
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5-5. Automatic Power Saving Mode There are four power saving modes defined in solid state disk(SSD) system. These four power saving modes are executed by firmware which use DSP's soft-hold and power down function and addition logic circuit to implement it. Active mode : In Active mode the SSD is capable of execution to file read and write operation. Idle mode : In Idle mode the SSD polls the events that include command_in or time_out events. If read/write command is asserted then the SSD will enter the Active mode. Standby mode : The SSD will enter the Standby mode after time_out(1.25ms) event occurs or standby command is asserted. The SSD controller MX9691L will enter soft_hold condition. The MX9619 will stop program execution and shut off most circuit activities to save many power comsumption. The MX9691L will automatically wake up and enter the Active mode if any command is asserted. Sleep mode : The SSD will enter the Sleep mode after sleep command is asserted. This is most power saving mode. The SSD controller MX9691L will enter soft _hold condition and stop main clock and then the all system activities will stop. This mode can be waked up by H/W reset, S/W reset or ATA command asserted. The H/W reset will reset all h/w circuits and the Host must reconfigure the SSD before any command is assseted. The S/W reset will set the busy status until the SSD is ready for accepting command, the Host don't need any h/w reinitialization. The duration of H/W and S/W reset must keep enough for main clock stabilization. The ATA command asserted to wake-up latency need the external RC circuit delay for clock stabilization while the Solid State Disk(SSD) had entered sleep mode.
Power Saving Flow
Power_up
Reset
Initialize Command_in
H/W Reset
Idle Exit Time-out1 or standby cmd S/W Reset Standby Command in Time-out2 or Sleep cmd Sleep Command in
Active
Wake-up latency
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5-6. Registers definition
* Registers List Type of Register PCMCIA/ATA Interface PC INTERRUPT CONTROL BUFFER MANAGER AND DMA ECC Control Flash Memory Interface * Register Description Port 6000h : Bit Function Description AT CONTROL/STATUS REGISTER Default reset value : 01h 7 R/W: DRIVE READY (drive 0) 6 R/W: DRIVE SEEK COMPLETE (drive 0) 5 R/W: CORRECTED DATA 4 R: ATA INT. ENABLE 3 R: AT SOFTWARE RESET 2 R/W: HOST INTERRUPT 1 R/W: ERROR BIT 0 R/W: BUSY BIT Port 6001h : Bit Function Description Default reset value : 00h 7:0 R/W: ERROR REGISTER (map to command block 1f1h) Port 6002h : Bit Function Description Default reset value : 01h 7:0 R/W: SECTOR COUNT REGISTER (map to command block 1f2h) Port 6003h : Bit Function Description Default reset value : 01h 7:0 R/W: SECTOR NUMBER REGISTER (map to command block 1f3h) Location 6000h, 6001h, 6002h, 6003h, 6004h, 6005h, 6006h, 6007h, 600Bh, 6010h, 6011h, 6012h, 6013h, 6019h, 601Ah, 601Bh, 601Ch 6009h, 600Ah 6008h, 6014h, 6015h, 6016h, 6017h, 6018h 600Ch, 600Dh, 600Eh, 600Fh 601Dh, 601Eh, 601Fh
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Port 6004h : Bit Function Description Default reset value : 00h 7:0 R/W: CYCLINDER LOW REGISTER (map to command block 1f4h) Port 6005h : Bit Function Description Default reset value : 00h 7:0 R/W: CYCLINDER HIGH REGISTER (map to command block 1f5h) Port 6006h : Bit Function Description Default reset value : A0h 7:0 R/W: DRIVE/HEAD REGISTER (map to command block 1f6h) Port 6007h : Bit Function Description Default reset value : 00h 7:0 R: COMMAND REGISTER (map to command block 1f7h) Port 6008h : Bit Function Description BUFFER RAM SIZE CONTROL REGISTER Default reset value : 40h 7 R/W: TEST MODE 1 for HAP/DAP test 0 : DISABLE 1 : ENABLE 6 R/W: BIT WRITE GATE STATE OF DRIVE 0 : ENABLE 1 : DISABLE 5 R: PCMCIA or True IDE mode 0 : True IDE mode 1 : PCMCIA mode 4 R/W: Auto DAP increment 0 : Disable 1 : Enable 3 R/W: Shadow ROM control 0 : Disable 1 : Enable 2:0 R/W: BUFFER RAM SIZE CONTROL 00x : 32KW 010 : 16KW 011 : 8KW 100 : 4KW 101 : 2KW 110 : 1KW
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111 : 512W Port 6009h : Bit Function Description HOST INTERRUPT STATUS Default reset value : 00h 7 6 5 4 3 2 1 0 R: Power-Down timer time-out detected R: Card configuration register write detected R: CIS accessed detected R: Hreset detected R: PC SRST(or PCMCIA SRST) DETECTED R: PC STATUS READ DETECTED R: PC SELECTION R: PC TRANSFER DONE
Port 600Ah : Bit Function Description HOST INTERRUPT ENABLE Default reset value : 00h 7 6 5 4 3 2 1 0 R/W: Power-Down timer time-out detected enable. R/W: Card configuration register write detected enable R/W: CIS accessed detected enable R/W: Hreset detected enable R/W: PC SRST(PCMCIA SRST) DETECTED ENABLE R/W: PC STATUS READ DETECTED ENABLE R/W: PC SELECTION ENABLE R/W: PC TRANSFER DONE ENABLE
Port 600Bh : Bit Function Description Default reset value : 00h 7:0 R: Feature register (map to command block 1f1h)
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Port 600Ch : Bit Function Description ECC CONTROL REGISTER Default reset value : 00h 7 R/W: ECC FUNCTION SUSPEND 0 : NORMAL 1 : SUSPEND 6 R/W: CORRECTION SPEED SELECT 0 : FULL SPEED (Max. Clock frequency) 1 : HALF SPEED (1/2 Max. Clock frequency) 5 R/W: ENCODE/DECODE FUNCTION SELECTION 0 : ENCODE 1 : DECODE 4 R/W: RESET ECC CIRCUIT 0 : RESET 1 : NORMAL 3 R: UNCORRECTABLE ERROR FLAG 2 R: CORRECTABLE ERROR FLAG 1 R: CORRECTION DONE FLAG 0 R/W: START ECC CORRECT FUNCTION ENABLE/DISABLE 0 : DISABLE 1 : ENABLE Port 600Dh : Bit Function Description Default reset value : 0000h 15:0 R/W : ECC 0 REGISTER Port 600Eh : Bit Function Description Default reset value : 0000h 15:0 R/W : ECC 1 REGISTER Port 600Fh : Bit Function Description Default reset value : 0000h 15:0 R/W : ECC 2 REGISTER Port 6010h : Bit Function Description Default reset value : 00h
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7:0 R: Configuration Option register (map to attribute memory 200h) Port 6011h : Bit Function Description Default reset value : 00h 7:0 R: Card Configuration and status register (map to attribute memory 202h) Port 6012h : Bit Function Description Default reset value : 0Ch 7:0 R: Pin replacement register (map to attribute memory 204h) Port 6013h : Bit Function Description Default reset value : 00h 7:0 R: Socket and copy register (map to attribute memory 206h) Port 6014h : Bit Function Description Default reset value : 0000h 15:0 R/W : HOST ADDRESS POINTER Port 6015h : Bit Function Description Default reset value : 00ffh 15:0 R/W : AT STOP POINTER Port 6016h : Bit Function Description Default reset value : 0000h 15:0 R/W : DISK ADDRESS POINTER Port 6017h : Bit Function Description DMA CONTROL REGISTER Default reset value : 08h 7 R/W: DRIVE READY (drive 1) 6 R/W: DRIVE SEEK COMPLETE (drive 1) 5 R/W: set BSY upon XFER done 0 : DISABLE 1 : ENABLE 4 R/W: ENABLE AUTO INTERRUPTS - AT ONLY 0 : DISABLE
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1 : ENABLE Port6017h: Bit Function Description 3 R/W: BUFFER RAM CHIP ENABLE 0 : ENABLE 1 : DISABLE 2 R/W: HOST BUS DIRECTION 0 : START BUFFER ---> AT BUS 1 : START AT BUS ---> BUFFER WHEN SET 1 R: A COMPLETION OF AT DMA XFER 0 R/W: START DATA TRANSFER BETWEEN AT BUS AND BUFFER RAM 0 : DISABLE 1 : ENABLE Port 6018h : Bit Function Description 15:0 R/W : ACCESS PORT INTO BUFFER RAM Port 6019h : Bit Function Description PCMCIA control register 7 R: True IDE mode 6 R: Common memory mode 5 R: I/O mode 4 R/W: host ready 3 R/W: no drive address 2 R/W: Internal registers write pulse width 0 : 2 system clock 1 : 1 system clock 1 R/W: Reserved.
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0 R/W: Reserved.
Port 601Ah : Bit Function Description Auxi_ctl_1 reg. Default reset value : 00h 7 6 R/W : DASP R/W : Host Interrupt level mode or pulse mode select 0: Level mode 1: Pulse mode R/W : PDIAG R/W : DASP output enable R/W: write protect enable 0: Disable 1: Enable R/W: PDIAG output enable R/W: master/slave mode enable 0: Disable 1: Enable R/W: master/salve of True IDE mode 0: master 1: slave
5 4 3
2 1
0
Port 601Bh : Bit Function Description Auxi_ctl_2 reg. Default reset value : 00h 7:4 3 2 Reserved. R/W: Reserved. R/W: Deep power down control for automatic wake-up function from sleep mode. 0 : Disable 1 : Enable R/W: Reserved. R/W: Disk interrupt polarity 0: Low active
1 0
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1: High active Port 601Ch : Bit Function Description Auxi_ctl_3 reg. Default reset value : 0000h 15 14 Reserved. R/W : Test mode 2 for timer 0 : Normal mode 1 : Test mode enable R : DRQ R : Time out status 1 : Time out event occurence R/W: Timer enable/disable 0 : Disable 1 : Enable R/W: Power-down timer time-out select for 25MHz main clock 00 : 16 x 1.28 = 20.48 sec. 01 : 8 x 1.28 = 10.24 sec. 10 : 4 x 1.28 = 5.12 sec. 11 : 2 x 1.28 = 2.56 sec. R : ICE-debugging mode detected 0 : ICE-debugging mode 1 : Free-run mode. R/W : Inverted data bus for access flash memory. 0 : Inverted. 1 : Non-inverted. R: External ROM detect. 0: Firmware stored in external ROM. 1: Firmware stored in linear type flash memory array. R/W: Shadow ROM space control 00 : 512 bytes, Range: 7400h ~ 74ffh 01 : 1Kbytes, Range: 7400h ~ 75ffh 10 : 1.5Kbytes, Range: 7400h ~ 76ffh 11 : 2Kbytes, Range: 7400h ~ 77ffh R : Master/Slave mode detect in True IDE mode 00 : Master of two drives 10 : Slave of two drives 11 : One drive R/W: PIO/DMA mode select 0: PIO mode.
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10:9
8
7
6
5:4
3:2
1
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0 Port 601Dh : Bit Function Description Default reset value : 0000h 9:0 R/W : Flash memory Read address FA[24:15] latch in linear mode When data space 8000h ~ ffffh is read, the output of the flash memory read address latch will be used. The definitions for this register in series mode Default reset value : 0000h 9 Reserved. 8 Bank select in capacity extension mode 0 : Bank0 selected. 1 : Bank1 selected. 7:5 R/W: FCE select for series mode 000: FCE0 001: FCE2 010: FCE4 011: FCE6 100: FCE1 101: FCE3 110: FCE5 111: FCE7 4 R/W: Command latch enable (FA19/CLE) 0 : Disable 1 : Enable 3 R/W: Address latch enable (FA18/ALE) 0 : Disable 2:0 1 : Enable Reserved 1: DMA mode. R/W: LED output
Port 601Eh : Bit Function Description Flash memory control register Default reset value : 08Ah 7 R/W: Flash memory deep power down control 0 in linear mode or Write protect in series mode 0 : Enable 1 : Disable 6 R : Ready / Busy status
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0 : BUSY 1 : READY Port 601Eh : Bit Function Description 5:4 R/W: Flash memory type select 00 : Reserved. 01 : 16M flash memory /Bank 1 select in linear mode or capacity extension mode selected in series mode. 10 : Reserved 11 : Reserved 3 R/W: Flash memory deep power down control 1 in linear mode or Spare area enable in series mode. 0 : Enable 1 : Disable 2 R/W: CE# enable for series mode 0 : Disable 1 : Enable 1 R/W: Series or linear mode select 0 : linear mode 1 : Series mode 0 R/W: Flash memory write pulse width control 0 : 1 system clock 1 : 2 system clock Port 601Fh : Bit Function Description Default reset value : 0000h 9 R/W : Flash memory Write address FA[24:15] latch in linear mode When data space 8000h ~ ffffh is write or program space 8000h ~ ffffh is read, the output of the flash memory write address latch will be used. The definitions for this register in series mode Reserved. 8 Bank select in capacity extension mode 0 : Bank0 selected. 1 : Bank1 selected. 7:0 Reserved.
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6. ELECTRICAL SPECIFICATIONS
6-1. DC Characteristics 1 : Ta = 0 oC to 70 oC, VCC = 5V10% Symbol VCC VIL1 VIH1 VIL2 VIH2 VOL VOH ICC1 ICC2 ICC3 ICC4 IL CIN COUT Parameter Power Supply voltage Input Low voltage (TTL) Input High voltage (TTL) Input Low voltage (CMOS) Input High voltage (CMOS) Output Low voltage Output High voltage Supply Current 1 Supply Current 2 Supply Currect 3 Supply Current 4 Input Leakage Input Capacitance Output Capacitance Min 4.5 2.0 1.2 3.5 0.4 2.5 40 30 12 1 10 14 16 Max 5.5 0.8 Units V V V V V V V mA mA mA mA uA pf pf Conditions VCC=5V VCC=5V VCC=5V VCC=5V IOL=8mA IOH=-8mA f=25Mhz, Active mode, CL=0pf, VCC=5.5Volt, Temperature= 0oC f = 25Mhz, Idle mode, CL = 0pf, VCC=5.5Volt, Temperature= 0oC f = 25Mhz, Standby mode, CL = 0pf, VCC=5.5Volt, Temperature= 0oC f = 0Mhz, Sleep mode, CL = 0pf, VCC=5.5Volt, Temperature= 0oC 0< VIN < VCC VIN=0V VOUT=0V
Note : During transitions, inputs may undershoot to -2.0V for periods less than 20ns and overshoot to VCC + 2.0V for periods less than 20ns.
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6-2. DC Characteristics 2 : Ta = 0 oC to 70 oC, VCC = 3.3V5% Symbol VCC VIL1 VIH1 VIL2 VIH2 VOL VOH ICC1 ICC2 ICC3 ICC4 IL CIN COUT Parameter Power Supply voltage Input Low voltage(TTL) Input High voltage(TTL) Input Low voltage(CMOS) Input High voltage(CMOS) Output Low voltage Output High voltage Supply Current 1 Supply Current 2 Supply Currect 3 Supply Current 4 Input Leakage Input Capacitance Output Capacitance Min 3.1 2.0 0.9 2.7 0.4 2.2 20 15 5 0.5 10 14 16 Max 3.5 0.8 Units V V V V V V V mA mA mA mA uA pf pf Conditions VCC=3.3V VCC=3.3V VCC=3.3V VCC=3.3V IOL=4mA IOH=-4mA f=16Mhz, Active mode, CL=0pf, VCC=3.5Volt, Temperature= 0oC f = 16Mhz, Idle mode, CL = 0pf, CC=3.5Volt, Temperature= 0oC f = 16Mhz, Standby mode, CL = 0pf, VCC=3.5Volt, Temperature= 0oC f = 0Mhz, Sleep mode, CL = 0pf, VCC=3.5Volt, Temperature= 0oC 0< VIN < VCC VIN=0V VOUT=0V
Note : During transitions, inputs may undershoot to -2.0V for periods less than 20ns and overshoot to VCC + 2.0V for periods less than 20ns.
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6-3. AC Characteristics Condition : Ta=0 oC to 70 oC, VCC = 5V10% or VCC = 3.3V5% (1). DSP Interface Timing : VCC = 5V10% Symbol Description Tw In ICE mode, WR# pulse duration when the data are accessed by external DSP. Trd In ICE mode, RD# to output delay when the data are accessed by external DSP. Tcs Chip select access cycle Taa Address access cycle Trds Data setup time before RD# high Tdh Data hold time after RD# high VCC = 3.3V5% Symbol Description Tw In ICE mode, WR# pulse duration when the data are accessed by external DSP. Trd In ICE mode, RD# to output delay when the data are accessed by external DSP. Tcs Chip select access cycle Taa Address access cycle Trds Data setup time before RD# high Tdh Data hold time after RD# high
Min. 4Tc
Typ.
Max.
Units
34 1.5Tc 1.5Tc 12 0 4.5Tc 4.5Tc
ns ns ns ns ns
Min. 4Tc
Typ.
Max.
Units
34 1.5Tc 1.5Tc 4.5Tc 4.5Tc
ns ns ns ns ns
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A[15:0] DCE#
WR#
Tw
D[15:0]
A[15:0] DCE#
RD#
Trd
D[15:0]
DCE#/PCE#
Tcs Taa
A[15:0]
RD#
D[15:0]
Trds
Tdh
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(2). Power Reset Timing VCC = 5V10% or VCC = 3.3V5% Symbol Description Tw(rst) Reset low pulse width (3). Clock Timing VCC = 5V10% Symbol Description Tc(c) Clock cycle time Tlpd(c) Clock low pulse duration(Tc=40ns) Thpd(c) Clock high pulse duration(Tc=40ns) VCC = 3.3V5% Symbol Description Tc(c) Clock cycle time Tlpd(c) Clock low pulse duration(Tc=62.5ns) Thpd(c) Clock high pulse duration(Tc=62.5ns) Min. 3Tc Typ. Max. Units ns
Min. 40 16 16
Typ.
Max. 24 24
Units ns ns ns
Min. 62.5 25 25
Typ.
Max. 37.5 37.5
Units ns ns ns
CLK IN Thp PWR RST# Tc Tw(rst) Tlpd
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(4). Interrupt Timing VCC = 5V10% Symbol Description Tw INT1# low pulse duration Tf INT1# fall time VCC = 3.3V5% Symbol Description Tw INT1# low pulse duration Tf INT1# fall time
Min. 1.5Tc
Typ.
Max. 10
Units ns ns
Min. 1.5Tc
Typ.
Max.
Units ns ns
(5). HOLD# Timing VCC = 5V10% or VCC = 3.3V5% Symbol Description Td(al-h) HLDA# low to address tri-state Td(hh-ha) HOLD# high to HLDA# high Ten(ah-a) Address driven after HLDA# high
Min. 0 0 0.5Tc-10
Typ. 0.5Tc 0.5Tc
Max. 0.5Tc+10 Tc
Units ns ns ns
INT1
Tf Tw Td(hh-ha)
HOLD# HLDA# Td(al-h) A[15:0]
Ten(ah-a)
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(6). PCMCIA Bus Timing 1: Common Memory and Attribute memory Access Timing VCC = 5V10% Symbol T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 VCC = 3.3V5% Symbol T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
Parameter Read cycle time Chip enable setup time before output enable Output data enable time from HOE# Chip disable hold time following output disable Output data disable time following HOE# Write cycle time Chip enable setup time before HWE# Write pulse width of HWE# Chip disable hold time following write disable Data setup time before HWE# Data hold time following HWE#
Min (ns) 60 0 1.5
Max (ns)
31 10.5 60 0 40 2 0 2.5
Parameter Read cycle time Chip enable setup time before output enable Output data enable time from HOE# Chip disable hold time following output disable Output data disable time following HOE# Write cycle time Chip enable setup time before HWE# Write pulse width of HWE# Chip disable hold time following write disable Data setup time before HWE# Data hold time following HWE#
Min (ns) 90 0 3
Max (ns)
47 17 90 0 60 2.5 0 3
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Common Memory and Attribute Memory Read Timing
T1 HA[10:0] REG# CE[2:1]# T2 HOE# T4 T3 T5 HD[15:0]
Common Memory and Attribute Memory WriteTiming
T6 HA[10:0] REG# CE[2:1]# T7 HWE# T11 HD[15:0] T8 T9
T10
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(7). PCMCIA Bus Timing 2: I/O mode Access Timing VCC = 5V10% Symbol T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24
Parameter Address hold time following IOR# REG# setup time before IOR# REG# hold time following IOR# CE# setup time before IOR# IOR# pulse width CE# hold time following IOR# Address setup time before IOR# INPACK delay from IOR# falling edge INPACK delay from IOR# rising edge IOIS16 falling delay after Address changed Data delay after IOR# falling IOIS16 rising delay after Address changed Data hold time following IOR# Address hold time following IOW# REG# setup time before IOW# REG# hold time following IOW# CE# setup time before IOW# IOW# pulse with CE# hold time following IOW# Address setup time before IOW# IOIS16 rising delay after Address changed IOIS16 falling delay after Address changed Data setup time before IOW# Data hold time following IOW#
Min (ns) 2 0 0 0 60 2 0
Max (ns)
10 10.5 14 32 12.5 20 3 0 0 0 60 2 0 10.5 14 0 2.5
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VCC = 3.3V5% Symbol T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 Parameter Address hold time following IOR# REG# setup time before IOR# REG# hold time following IOR# CE# setup time before IOR# IOR# pulse width CE# hold time following IOR# Address setup time before IOR# INPACK delay from IOR# falling edge INPACK delay from IOR# rising edge IOIS16 falling delay after Address changed Data delay after IOR# falling IOIS16 rising delay after Address changed Data hold time following IOR# Address hold time following IOW# REG# setup time before IOW# REG# hold time following IOW# CE# setup time before IOW# IOW# pulse with CE# hold time following IOW# Address setup time before IOW# IOIS16 rising delay after Address changed IOIS16 falling delay after Address changed Data setup time before IOW# Data hold time following IOW# Min (ns) 2 0 0 0 90 2 0 Max (ns)
18 18 23.5 47 20 31 4 0 0 0 90 2.5 0 20 23.5 0 3
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MX9691L
ID Read Timing
HA[10:0] T1 REG# T2 T4 CE[2:1]# IOR# T7 INPACK# IOIS16# T10 HD[15:0] T11 T12 T8 T5 T9 T6 T3
T13
I/O Write Timing
HA[10:0] T14 REG# T15 T17 CE[2:1]# IOW# T20 T21 IOIS16# T22 HD[15:0] T19 T18 T16
T23
T24
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(8). Flash Memory Interface Timing VCC = 5V10% Symbol Tw(a-ce) Twas Tw(wrflash) Tr(a-ce) Tr(rd-oe) VCC = 3.3V5% Symbol Tw(a-ce) Twas Tw(wrflash) Tr(a-ce) Tr(rd-oe)
Parameter FCE# fall time after DSP address decode when write FCE# setup time before WRFLASH# falling edge WRFLASH# low pulse duration FCE# fall time after DSP address decode when read RDFLASH# fall time after RD# falling edge
Min 5.5 10 1Tc * 5.5 4.5
Max 15 29.5 15 11.5
Units ns ns ns ns ns
Parameter FCE# fall time after DSP address decode when write FCE# setup time before WRFLASH# falling edge WRFLASH# low pulse duration FCE# fall time after DSP address decode when read RDFLASH# fall time after RD# falling edge
Min 8 14.5 1Tc * 8 6.5
Max 24.5 49 24.5 20
Units ns ns ns ns ns
[* Note]: Theses timing are only for 1-system clock of flash memory write pulse is employed (601E[0]=0). If 2-system clock of pulse width is selected (601E[0]=1), the minimum time of Tw(wrflash) is 2Tc.
Flash memory write timing
A[15:0] Tw(a-ce) FCE[7:0] WR# Twas Tw(wrflash) WRFLASH#
Flash memory Read timing
A[15:0] Tr(a-ce) FCE[7:0] RD# Tras
RDFLASH#
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6-4. Latchup Characteristics Min. Input Voltage with respect to GND on all VCC pins -2.0V Input Voltage with respect to GND on all I/O pins -2.0V Current -100mA Includes all pins expect GND. Test conditions:VCC=5.0V, one pin at a time. Max. 12.0V VCC+2.0V +100mA
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REVISION HISTORY Revision 1.1 Destription Modify package type Page P1 Date JUL/02/1999
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MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-6688 FAX:+886-3-563-2888
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TEL:+32-2-456-8020 FAX:+32-2-456-8021
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TEL:+1-847-963-1900 FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
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